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HM-65162
March 1997
2K x 8 Asynchronous CMOS Static RAM
Description
The HM-65162 is a CMOS 2048 x 8 Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle time and ease of use. The pinout is the JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which allows easy memory board layouts flexible to accommodate a variety of industry standard PROMs, RAMs, ROMs and EPROMs. The HM-65162 is ideally suited for use in microprocessor based systems with its 8-bit word length organization. The convenient output enable also simplifies the bus interface by allowing the data outputs to be controlled independent of the chip enable. Gated inputs lower operating current and also eliminate the need for pull-up or pull-down resistors.
Features
* Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/90ns Max * Low Standby Current. . . . . . . . . . . . . . . . . . . .50A Max * Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max * Data Retention at 2.0V . . . . . . . . . . . . . . . . . . .20A Max * TTL Compatible Inputs and Outputs * JEDEC Approved Pinout (2716, 6116 Type) * No Clocks or Strobes Required * Equal Cycle and Access Time * Single 5V Supply * Gated Inputs * No Pull-Up or Pull-Down Resistors Required
Ordering Information
PACKAGE CERDIP JAN# SMD# CLCC SMD# NOTE: 1. Access time/data retention supply current. TEMP. RANGE -40oC to +85oC -55oC to +125oC -55oC to +125oC -40oC to +85oC -55oC to 125oC 70ns/20A (NOTE 1) HM1-65162B-9 29110BJA 8403606JA HM4-65162B-9 8403606ZA 90ns/40A (NOTE 1) HM1-65162-9 29104BJA 8403602JA HM4-65162-9 8403602ZA 8403603JA HM4-65162C-9 8403603ZA 90ns/300A (NOTE 1) HM1-65162C-9 PKG. NO. F24.6 F24.6 F24.6 J32.A J32.A
Pinouts
HM-65162 (CERDIP) TOP VIEW
NC A7
HM-65162 (CLCC) TOP VIEW
VCC
PIN
NC NC 31 30 29 A8 28 A9 27 NC 26 W 25 G 24 A10 23 E 22 DQ7 21 DQ6
DESCRIPTION No Connect Address Input Chip Enable/Power Down Ground Data In/Data Out Power (+5V) Write Enable Output Enable
NC
NC
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
1 2 3 4 5 6 7 8 9
24 VCC 23 A8 22 A9 21 W 20 G 19 A10 18 E 17 DQ7 16 DQ6 15 DQ5 14 DQ4 13 DQ3 A6 A5 A4 A3 A2 5 6 7 8 9
4
3
2
1
32
NC A0 - A10 E VSS/GND DQ0 - DQ7 VCC W G
A1 10 A0 11 NC 12 DQ0 13 14 DQ1 15 16 DQ2 GND 17 NC 18 DQ3 19 DQ4 20 DQ5
DQ1 10 DQ2 11 GND 12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3000.1
6-1
HM-65162 Functional Diagram
A1 A A2 A3 A4 A5 A6 A7 ROW ADDRESS BUFFER 7 ROW DECODER A 7 128 COLUMN DECODER AND DATA INPUT / OUTPUT (X8) 4 A G 4 A 1 OF 8 DQ0 THRU DQ7 128 128 X 128 MEMORY ARRAY
8
E
COLUMN ADDRESS BUFFER
W
A0
A8 A9 A10
6-2
HM-65162
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . 05mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 48 8 CLCC Package . . . . . . . . . . . . . . . . . . 66 12 Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-65162S-9, HM-65162B-9, HM-65162-9, HM65162C-9. . . . . . . . . . . . . . . . . . -40oC to +85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26000 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
SYMBOL ICCSB1
VCC = 5V 10%; TA = -40oC to +85oC (HM-65162S-9, HM-65162B-9, HM-65162-9, HM-65162C-9) LIMITS
PARAMETER Standby Supply Current
MIN -
MAX 50 100
UNITS A A
TEST CONDITIONS HM-65162B-9, IO = 0mA, E = VCC - 0.3V, VCC = 5.5V HM-65162S-9, HM65162-9, IO = 0mA, E = VCC - 0.3V, VCC = 5.5V HM-65162C-9, IO = 0mA, E = VCC - 0.3V, VCC = 5.5V E = 2.2V, IO = 0mA, VCC = 5.5V E = 0.8V, IO = 0mA, VCC = 5.5V E = 0.8V, IO = 0mA, f = 1MHz, VCC = 5.5V HM-65162B-9, IO = 0mA, VCC = 2.0V, E = VCC - 0.3V HM-65162S-9, HM-65162-9, IO = 0mA, VCC = 2.0V, E = VCC - 0.3V HM-65162C-9, IO = 0mA, VCC = 2.0V, E = VCC - 0.3V VI = VCC or GND, VCC = 5.5V VIO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 4.0mA, VCC = 4.5V IO = -1.0mA, VCC = 4.5V IO = -100A, VCC = 4.5V
ICCSB ICCEN ICCOP ICCDR Standby Supply Current Enabled Supply Current Operating Supply Current (Note 1) Data Retention Supply Current -
900 8 70 70 20 40
A mA mA mA A A
VCCDR II IIOZ VIL VIH VOL VOH1 VOH2 Data Retention Supply Voltage Input Leakage Current Input/Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage (Note 2) TA = +25oC PARAMETER Input Capacitance (Note 2) Input/Output Capacitance (Note 2) MAX 10 12 2.0 -1.0 -1.0 -0.3 2.2 2.4 VCC -0.4
300 +1.0 +1.0 0.8 VCC +0.3 0.4 -
A V A A V V V V V
Capacitance
SYMBOL CI CIO NOTES:
UNITS pF pF
TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes.
6-3
HM-65162
AC Electrical Specifications
VCC = 5V 10%, TA = -40oC to +85oC (HM-65162S-9, HM-65162B-9, HM65162-9, HM-65162C-9)
LIMITS HM-65162S-9 SYMBOL READ CYCLE (1) TAVAX (2) TAVQV (3) TELQV (4) TELQX (5) TGLQV (6) TGLQX (7) TEHQZ (8) TGHQZ (9) TAVQX WRITE CYCLE (10) TAVAX (11) TELWH (12) TAVWL (13) TWLWH (14) TWHAX (15) TGHQZ (16) TWLQZ (17) TDVWH (18) TWHDX (19) TWHQX (20) TWLEH (21) TDVEH (22) TAVWH Write Cycle Time Chip Selection to End of Write Address Setup Time Write Enable Pulse Width Write Enable Read Setup Time Output Enable Output Disable Time Write Enable Output Disable Time Data Setup Time Data Hold Time Write Enable Output Enable Time Write Enable Pulse Setup Time Chip Enable Data Setup Time Address Valid to End of Write 55 45 5 40 10 25 10 0 45 25 45 30 30 70 45 10 40 10 30 10 0 40 30 50 35 40 90 55 10 55 10 30 15 0 55 30 65 40 50 90 55 10 55 10 30 15 0 55 30 65 40 50 ns ns ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable Output Enable Time Output Enable Access Time Output Enable Output Enable Time Chip Enable Output Disable Time Output Enable Output Disable Time Output Hold From Address Change 55 5 5 5 55 55 35 35 30 70 5 5 5 70 70 50 35 35 90 5 5 5 90 90 65 50 40 90 5 5 5 90 90 65 50 40 ns ns ns ns ns ns ns ns ns PARAMETER MIN MAX HM-65162B-9 MIN MAX HM-65162-9 MIN MAX HM-65162C-9 MIN MAX UNITS CONDITIONS
(Notes 1, 3) (Notes 1, 3, 4) (Notes 1, 3) (Notes 2, 3) (Notes 1, 3) (Notes 2, 3) (Notes 2, 3) (Notes 2, 3) (Notes 1, 3)
(Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 2, 3) (Notes 2, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3)
NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent and CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5 and 5.5V. 4. TAVQV = TELQV + TAVEL.
6-4
HM-65162 Timing Waveforms
(1) TAVAX (2) TAVQV ADDRESS (8) TGHQZ G (5) TGLQV E (6) TGLQX (3) TELQV Q (4) TELQX (9) TAVQX (7) TEHQZ
NOTE: 1. W is high for a Read Cycle. FIGURE 1. READ CYCLE
Addresses must remain stable for the duration of the read cycle. To read, G and E must be VIL and W VIH. The output buffers can be controlled independently by G while E is low. To execute consecutive read cycles, E may be tied
low continuously until all desired locations are accessed. When E is low, addresses must be driven by stable logic levels and must not be in the high impedance state.
(10) TAVAX ADDRESS (11) TELWH E (12) TAVWL W (16) TWLQZ Q (21) TDVEH D (13) TWLWH (20) TWLEH (19) TWHQX (14) TWHAX
(17) TDVWH (22) TAVWH
(18) TWHDX
NOTE: 1. G is low throughout Write Cycle. FIGURE 2. WRITE CYCLE I
To write, addresses must be stable, E low and W falling low for a period no shorter than TWLWH. Data in is referenced with the rising edge of W, (TDVWH and TWHDX). While addresses are changing, W must be high. When W falls low, the I/O pins are still in the output state for a period of TWLQZ
and input data of the opposite phase to the outputs must not be applied, (Bus contention). If E transitions low simultaneously with the W line transitioning low, or after the W transition, the output will remain in a high impedance state. G is held continuously low.
6-5
HM-65162 Timing Waveforms (Continued)
(10) TAVAX ADDRESS (22) TAVWH G (11) TELWH E (12) TAVWL W TGHQZ (15) Q (21) TDVEH D (17) TDVWH (18) TWHDX (13) TWLWH (14) TWHAX
FIGURE 3. WRITE CYCLE II
In this write cycle G has control of the output after a period, TGHQZ. G switching the output to a high impedance state allows data in to be applied without bus contention after
TGHQZ. When W transitions high, the data in can change after TWHDX to complete the write cycle.
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (E) must be held high during data retention; within VCC -0.3V to VCC +0.3V. 2. On RAMs which have selects or output enables (e.g., S, G), one of the selects or output enables should be held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation. 3. Inputs which are to be held high (e.g., E) must be kept between VCC +0.3V and 70% of VCC during the power up and down transitions. 4. The RAM can begin operation > 55ns after VCC reaches the minimum operating voltage (4.5V).
DATA RETENTION TIMING VCC VCC 02.0V
4.5V
4.5V >55ns
E
VCC -0.3V TO VCC +0.3V
FIGURE 4. DATA RETENTION TIMING
6-6
HM-65162 Typical Performance Curve
-3 -4 -5 LOG (ICC/(1A)) -6 -7 -8 -9 -10 -11 -12 -55 -35 -15 5 25 45 65 85 105 125 VCC = 2.0V
TA (oC)
FIGURE 5. TYPICAL ICCDR vs TA
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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